In integrated circuit fabrication, it is often desirable to allow a system whereby a user may customize an integrated circuit to their particular needs. Because of the great expense involved in designing specific integrated circuits for many specific tasks, programmable integrated circuits have been developed which allow the user to program the integrated circuit to their specific needs. An emerging type of programmable device is field programmable gate arrays (FPGAs). These devices provide large arrays of fusible type structures which allow the user to program the functional operation of the devices by altering the conductive state of these fusible devices. One such fusible device is called an anti-fuse. An anti-fuse operates in the opposite of the traditional meaning of the term "fuse". An anti-fuse is programmed by providing a voltage above a threshold determined by the characteristics of the device which causes a large current to pass through a dielectric layer between two conductive layers. After this threshold voltage has been reached, a conductive connection between the two conductive layers is permanently established. This is opposite the traditional meaning of a fuse in that when a high current is passed through a traditional fuse, the fuse is burned open and thus a conductive connection is broken. An example of the anti-fuse technology can be found in Mohsen, et. al., "Programmable Low Impedance Anti-fuse Element", U.S. Pat. No. 4,823,181 issued Apr. 18, 1989. This patent is hereby incorporated by reference. A field programmable gate array structure which utilizes anti-fuse elements is described in Gamal et. al., "An Architecture For Electrically Configurable Gate Arrays", IEEE Journal of Solid State Circuits, Vol. 24, No. 2, Pgs. 394-398, (April 1989). This article is hereby incorporated by reference.
As in all integrated circuits, it is desirable to provide a circuit which operates as rapidly as possible. Prior art anti-fuse structures provide horizonal areas which are limited by the lithography capabilities used to fabricate the integrated circuit. These devices are in arrays with a very thin dielectric (60-200 .ANG. as disclosed in the Mohsen, et. al. patent). Because these dielectrics must be very thin, a very high capacitance is provided between the conductive leads forming the gate array. In addition, because there are many of these devices along a particular lead, the resistive/capacitive (RC) time constant for a particular lead is very high. This creates a very large time lag from when a voltage is applied to a certain lead until the lead is charged up to the desired voltage. Thus it is desirable to minimize the capacitive coupling provided by an anti-fuse element. In addition, it is desirable to minimize the lateral area covered by anti-fuse structure to allow for greater packing density of anti-fuse elements. This allows for shorter conductive leads for the same amount of anti-fuse elements as compared to the prior art structures. Because the anti-fuse leads are shorter, the resistance along the length of the lead is minimized and the RC constant is further reduced.